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application the connor-winfield mstm-s3-tr simplified control timing module acts as a complete system clock module for stratum 3 timing applications in accordance with gr- 1244, issue 2 and gr-253, issue 3. connor winfield?s stratum 3 timing modules helps reduce the cost of your design by minimizing your development time and maximizing your control of the system clock with our simplified design. features ? 5v miniature timing module redundant references 2 synchronous outputs available from 8 khz to 77.76mhz 40 sec., filtered, hold over history operational status flags mstm-s3-tr stratum 3 timing module 2111 comprehensive drive aurora, illinois 60505 phone: 630- 851- 4722 fax: 630- 851- 5040 www.conwin.com bulletin tm027 page 1 of 16 revision p02 date 14 august 01 issued by mbatts
data sheet #: tm027 p age 2 of 16 rev: p02 date: 08 / 14 / 01 ? copyright 2001 the connor-winfield corp. all rights reserved specifications subject to change without notice general description the connor-winfield stratum 3 simplified control timing mod- ule acts as a complete system clock module for general stratum 3 timing applications. the mstm is designed to replace similar units from tf systems (tf118b) and raltron (sy0001b). full external control input allows for selection and monitoring of any of four possible operating states: 1) holdover, 2) external reference #1, 3) external reference #2, and 4) free run. table #1 illustrates the control signal inputs and corresponding opera- tional states. in the absence of external control inputs (a,b), the mstm enters the free run mode and signals an external alarm. the mstm will enter other operating modes upon application of a proper control signal. mode 1 operation (a=1, b=0) results in an output signal that is phase locked to the external reference input #1. mode 2 operation (a=0, b=1) results in an output sig- nal that is phase locked to external reference input #2. hold- over mode operation (a=1, b=1) results in an output signal at or near the frequency as determined by the latest (last) locked- signal input values and the holdover performance of the mstm. free run modefree run mode operation (a=0, b=0) is a guar- anteed output of 4.6 ppm of the nominal frequency. alarm signals are generated at the alarm output during hold- over and free run operation. alarm signals are also generated by loss-of-lock, loss of reference, and by a tune-limit indication from the pll. a tune-limit alarm signal indicates that the vcxo tuning voltage is approaching within 10% the limits of its lock capability and that the external reference input may be errone- ous. a high level indicates an alarm condition. real-time indica- tion of the operational mode is available at unique operating mode outputs on pins 1-4. control loop 0.1 hz filters effectively attenuate any reference jitter, smooth out phase transients, comply with wander transfer and jitter tolerances. absolute maximum rating table 2 symbol parameter minimum nominal maximum units notes v cc power supply voltage -0.5 7.0 volts 1.0 v i input voltage -0.5 v cc + 0.5 volts 1.0 t s storage temperature -55 100 deg. c 1.0 functional block diagram figure 1 1 2 3 4 free run ref #1 ref #2 hold over cntl a cntl b opt_out sync_out ex ref 1 ex ref 2 pll_tvl free run hold over lol & lor alarm_out ? n dpll cntl cntl operational ref 1 ref 2 hold over free run pll_tvl alarm out a b mode 0 0 free run (default mode) 0 0 0 1 0 1 external normal 1 0 0 0 0 0 1 0 reference tune limit 1 0 0 0 1 1 #1 lor + lol 1 0 0 0 0 1 external normal 0 1 0 0 0 0 0 1 reference tune limit 0 1 0 0 1 1 #2 lor + lol 0 1 0 0 0 1 1 1 hold over 0 0 1 0 0 1 function control table table 1
data sheet #: tm027 p age 3 of 16 rev: p02 date: 08 / 14 / 01 ? copyright 2001 the connor-winfield corp. all rights reserved specifications subject to change without notice notes: 1.0: stresses beyond those listed under absolute maximum rating may cause damage to the device. operation beyond recommended conditions is not implied. 2.0: logic is 3.3v cmos 3.0 gr-1244-core 3.2.1 recommended operating conditions table 3 symbol parameter minimum nominal maximum units notes v cc power supply voltage 4.75 5.00 5.25 volts v th reset threshold voltage 4.25 4.5 volts v ih high level input voltage - ttl 2.0 v cc volts v il low level input voltage - ttl 0 0.8 volts t in input signal transition - ttl 250 ns c in input capacitance 15 pf v oh high level output voltage, 2.4 5.25 volts 2.0 i oh = -4.0ma, v cc = min. v ol low level output voltage, 0.4 volts i ol = 12.0 ma, v cc = min. t trans clock out transition time 4.0 ns t pulse 8khz input reference pulse 30 ns width( positive or negative) t op operating temperature 0 70 c specifications table 4 parameter specifications notes frequency range (sync_out) 8 khz to 77.76 mhz frequency range (opt_out) 8 khz to 77.76 mhz supply current 250 ma typical, 400 ma during warm-up (maximum) timing reference inputs 8 khz - 19.44 mhz 3.0 jitter, wander and phase transient tolerances gr-1244-core 4.2-4.4, gr-253-core 5.4.4.3.6 wander generation gr-1244-core 5.3, gr-253-core 5.4.4.3.2 wander transfer gr-1244-core 5.4 jitter generation gr-1244-core 5.5, gr-253-core 5.6.2.3 jitter transfer gr-1244-core 5.5, gr-253-core 5.6.2.1 phase transients gr-1244-core 5.6, gr-253-core 5.4.4.3.3 free run accuracy 4.6 ppm over t op hold over stability 0.37 ppm for initial 24 hrs 4.0 inital offset 0.05 ppm temperature 0.28 ppm drift 0.04 ppm maximum hold over history 40 seconds pull-in/ hold-in range 13.8 ppm minimum 5.0 lock time 30 seconds maximum dpll bandwidth 0.1 hz pll_tvl alarm limit extreme 10% ranges of pull-in/hold-in range 4.0: hold over stability is the cumulative fractional frequency offset as described by gr-1244-core, 5.2 5.0: pull-in range is the maximum frequency deviation from nominal clock rate on the reference inputs to the timing module that can be overcome to pull into synchronization with the reference
data sheet #: tm027 p age 4 of 16 rev: p02 date: 08 / 14 / 01 ? copyright 2001 the connor-winfield corp. all rights reserved specifications subject to change without notice pin description table 5 pin # connection description 1 hold over indicator output. high output when hold over mode is selected by control pins. 2 ref 1 indicator output. high output when ref 1 mode is selected by control pins. 3 ref 2 indicator output. high output when ref 2 mode is selected by control pins. 4 free run indicator output. high output when free run mode is selected by control pins. 5 gnd ground 6 alarm _out alarm output. high output if module is in free run, or hold over, or lor, or lol, or pll_tvl mode. 7 cntl a mode control input 8 cntl b mode control input 9 pll_tvl tuning voltage limit alarm output. high output when sync_out is near the extreme 10% ranges of the pull-in/hold-in range. 10 tri-state/gnd 0 = normal operation, 1= tri-state. pin is pulled low internally. ground pin for normal operation. 11 sync_out primary timing output signal. signal is sychronized to reference. 12 gnd ground 13 opt_out secondary timing output signal. signal is derived directly from sync_out. 14 gnd ground 15 ex_ref_2 external input reference #2 16 gnd ground 17 ex_ref_1 external input reference #1 18 vcc +5v dc supply ordering information mstm-s3-tr-(input reference frequency)(opt_out frequency)-(primary output) 1= 1.544 mhz 2= 2.048 mhz 02.048m = 2.048mhz 2= 2.048 mhz 8= 8 khz 016.384m = 16.384 mhz 8= 8 khz s= other 019.44m = 19.44 mhz 9= 19.44 mhz 032.768m = 32.76 mhz s= other primary output / n 038.88 m = 38.88 mhz 077.76 m = 77.76 mhz example: mstm-s3-tr-88-038.88m
data sheet #: tm027 p age 5 of 16 rev: p02 date: 08 / 14 / 01 ? copyright 2001 the connor-winfield corp. all rights reserved specifications subject to change without notice typical application figure 2 typical system test set-up figure 3 ,qsxw 6hohfw 08; 08; 08; 08; 6\vwhp6hohfw %,76 6\vwhp 6ljqdo &:v6700670prgxoh &:v6700670prgxoh &:v6&* &:v6&* $ % 6 < $ % < 6 $ % $ % 6 < 6 < 7lplqj&dug 7lplqj&dug /lqh&dug 5&9 5&9 &orfn rxw &orfn rxw /lqh &dug 1 target system under test possible choices include stanford research model: fs700 truetim e model xxx arbitrary waveform generator external reference input arbitrary waveform generator [n o ise source] d s 1 rate r z (1.544 m hz), e 1 rate r z or 8 kh z c loc k r z w ith n ois e m od ula tio n tektronix sj300e clock or bits logic level clock input (ttl, cmos, etc.) hp53310a modulation analyzer / time interval analyzer ds 1 rate [1.544 m h z] b its b ipolar phase error data output sample w ander g eneration (t dev) for st m /mstm -s3 100.0e-12 1.0 e -9 10.0e-9 100.0e-9 1.0 e -6 10.0e-3 100.0e-3 1.0e+0 10.0e+0 100.0e+0 1.0e+3 integration time (sec) tdev (se c tdev gr1244-fig5.1 gr1244-fig5-3 t y p i c a l r e s p o n s e - 3 0 0 0 s e c o n d t e s t - j it t e r a p pl ie d ( 2 u i @ 1 0 h z ) ref date a p r 22 1998 kdh c o pyright 1998 c o nno r-w infield alll rights res erved s a m p le m t ie d a ta fo r s t m -s 3 /m s t m -s 3 1.0e-9 10.0e-9 100.0e-9 1.0e-6 100.0e-3 1.0e+0 10.0e+0 100.0e+0 1.0e+3 10.0e+3 o bserva tion tim e (s) m tie (s mtie 1 2 4 4 -5 .2 m a s k ( a ) 1 2 4 4 -5 .2 m a s k ( b ) 1 2 4 4 -5 .6 m a s k g r253-5 .4.4.3.2 c o pyright 1998 c o nno r-w infield all rights reserved t y p i c al r e s p o n s e - 3 0 0 0 s e c o n d t e s t - j it t e r a p p lie d (2 u i @ 1 0 h z ) ref date a p r 22 1998 kdh standards c om plia nc e documents time-stam ped ensem ble b as e d on a bs olu te tim e reference (10mhz input) ds-1, o c-3, oc-12 electrical or optical signals w ander analyzer data (ieee-488) 10 mhz t h is d evice su pp lies s ystem tim e inform ation. it can be thought of as supplying "absolute tim e" reference in fo rm a tio n 10 mhz external reference input noise modulation input 10 mhz external reference input ieee-488 controller p latfo rm fo r s oftw are hp 53305a phase analyzer hp e1748a sync measurem ent tektronix w ander analyzer 10 mhz external reference input timing card line card timing card oc-3 line card oc-12 line card oc-48 line card ds-1 line card . . . . ... m tie, tdev, w ander transfer, and w ander generation plots tektronix sj300e gps or loran tim ing source
data sheet #: tm027 p age 6 of 16 rev: p02 date: 08 / 14 / 01 ? copyright 2001 the connor-winfield corp. all rights reserved specifications subject to change without notice mstm-s3-tr typical current draw figure 4 typical calibrated wander transfer tdev figure 5 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0 102030405060 time (sec) current (a) 1 10 10 0 10 0 0 10000 in te g r a tio n t im e (s e c .) tdev (ns) tdev (ns) gr1244, fig 5.3
data sheet #: tm027 p age 7 of 16 rev: p02 date: 08 / 14 / 01 ? copyright 2001 the connor-winfield corp. all rights reserved specifications subject to change without notice typical wander generation mtie figure 6 10 100 1000 0.1 1 10 100 1000 10000 100000 1000000 o bservation tim e (sec.) mtie (ns) g r1244, fig 5.2 (a) g r1244, fig 5.2 (b) g r253-5.4.4.3.2, fig 5.17 m t ie (n s ) typical wander generation tdev figure 7 0.1 1 10 100 0.1 1 10 100 1000 10000 integration time (sec.) tdev (ns) tdev (ns) gr1244, fig 5.1
data sheet #: tm027 p age 8 of 16 rev: p02 date: 08 / 14 / 01 ? copyright 2001 the connor-winfield corp. all rights reserved specifications subject to change without notice typical phase transient mtie figure 9 1 10 100 1000 10000 0.01 0.1 1 10 100 1000 observation time (sec) mtie (ns) gr-253, fig. 5-19 m tie (ns) 1ms phase transient tie figure 8 -200 0 200 400 600 800 1000 1200 012345678910 time (sec) tie (ns)
data sheet #: tm027 p age 9 of 16 rev: p02 date: 08 / 14 / 01 ? copyright 2001 the connor-winfield corp. all rights reserved specifications subject to change without notice entry into hold over figure 10 1 10 100 1000 10000 0.001 0.01 0.1 1 10 100 observation tim e (seconds) mtie (ns) gr-1244 objective, fig. 5-8 gr-1244 requirem ent, fig. 5-8 ty pic al m tie return from hold over figure 11 1 10 100 1000 10000 0.001 0.01 0.1 1 10 100 observation tim e (sec.) mtie (ns) gr-1244 requirem ent, fig. 5-7 m tie (ns) typic al m tie
data sheet #: tm027 p age 10 of 16 rev: p02 date: 08 / 14 / 01 ? copyright 2001 the connor-winfield corp. all rights reserved specifications subject to change without notice 2 msec < t < 4.125 msec d m change in operational mode operational mode indicator d t m mstm-s3-tr mode indicator delay figure 12 tuning voltage limit alarm timing diagram figure 13 ? t tvl limit high frequency tvl limit low frequency sync_out tvl alarm & alarm out 0 < t < 2.125 msec *the dac is updated only when the output changes level. the maximum update rate is 8 khz ? (nominal frequency)
data sheet #: tm027 p age 11 of 16 rev: p02 date: 08 / 14 / 01 ? copyright 2001 the connor-winfield corp. all rights reserved specifications subject to change without notice loss of reference timing diagram figure 14 power on reset levels figure 15 v range th v cc normal operation reset reset external reference input alarm ton a toff a 2 msec < t on < 6.125 msec 0 msec < t off < 2.125 msec a a
data sheet #: tm027 p age 12 of 16 rev: p02 date: 08 / 14 / 01 ? copyright 2001 the connor-winfield corp. all rights reserved specifications subject to change without notice solder clearance figure 16 .030" pin land all solder and/or wire tags shall not extend more than .020" below pc board bottom surfac e .020" .020" max.
data sheet #: tm027 p age 13 of 16 rev: p02 date: 08 / 14 / 01 ? copyright 2001 the connor-winfield corp. all rights reserved specifications subject to change without notice
it is recommended that there be no vias or feed throughs underneath the main body of the module between the pins. it is suggested that the traces in this area be kept to a minimum and protected by a layer of solder mask. see figure 18. a solder mask is recommended to cover most the top pad to avoid excessive solder underneath the shoulder of the pin to avoid rework damage. see table 6 and figure 19.

the recommended pad construction is shown in figure 18. for the pin diameter of .040? a hole diameter of .055? is suggested for ease of insertion and rework. a pad diameter of .150? is also suggested for support. this leaves a spacing of .050? between the pads which is sufficient for most signal lines to pass through. the pins are arranged in a dual-in-line configuration as shown in figure 16. there is .2? space between the pins in-line and each line is separated by 1.6?. see figures 17 & 18 and table 6.
the mechanical outline of the mstm-s3-tr is shown in figure 17. the board space required is 2? x 2?. the pins are .040? in diameter and are .150? in length. the unit is spaced off the pcb by .030? shoulders on the pins. due to the height of the device it is recommended to have heat sensitive devices away where the air flow might not be blocked.
do not bakeout the mstm-s3-tr
the mstm-s3-tr is not in a hermetic enclosure. it is recommended that the leads be hand cleaned after soldering. do not completely immerse the module.
due to the sensitive nature of this part, hand soldering or wave soldering of the pins is recommended after reflow processes.
good power supply regulation is recommended for the mstm-s3-tr the internal oscillators are regulated to operate from 4.75 - 5.25 volts. large jumps within this range may still produce varying degrees of wander. if the host system is subject to large voltage jumps due to hot-swapping and the like, it is suggested that there be some form of external regulation such as a dc/dc converter. power specifications will vary depending primarily on the temperature range. at wider temperature ranges starting at 0 to 70 deg. c., an ovenized oscillator, ocxo, will be incorporated. the turn-on current for an ocxo requires a peak current of about .4a for about a minute. the steady state current will the vary from 50-150 ma depending on the temperature. it is suggested to plan for the peak current in the power and ground traces pin 18 and pin 5. the other four ground pins 10, 12, 14, and 16 are intended for signal grounds.
data sheet #: tm027 p age 14 of 16 rev: p02 date: 08 / 14 / 01 ? copyright 2001 the connor-winfield corp. all rights reserved specifications subject to change without notice package dimensions figure 17 0.200 [5.08 mm] 0.555 [14.10 mm] 0.200 [5.08 mm] 1.600 [40.64 mm] 2.000 [50.80 mm] 0.200 [5.08 mm] 2.000 [50.80 mm] 0.585 [14.86 mm] maximum height 0.200 [5.08 mm] 0.078 [1.98 mm] 0.040 [1.02 mm] 0.120 [3.05 mm] 0.045 [1.14 mm] recommended footprint dimensions figure 18 side assembly view figure 19 characteristic measurements table 6 characteristic item measurement (inches) pad to pad spacing 0.200 solder pad top o.d. 0.150 solder pad top i.d. 0.055 solder pad bottom o.d. 0.150 solder pad bottom i.d. 0.055 solder mask top dia. 0.070 solder mask bottom dia. 0.155 pin row to row spacing 1.600 1.600 i.d. ? 0.055 finished hole o.d. ? 0.150 copper pad via keepout area 2 . 0 0 0 2.000 0.200 0 . 2 0 0 pin #1 pin #18 0 . 2 0 0 top side solder resist (over pad) pcb side view bottom side solder resist (up to pad)
data sheet #: tm027 p age 15 of 16 rev: p02 date: 08 / 14 / 01 ? copyright 2001 the connor-winfield corp. all rights reserved specifications subject to change without notice revision revision date note p00 7/27/01 preliminary release p01 8/01/01 added por figure and tri-state pin p02 8/14/01 added new input frequency
2111 comprehensive drive aurora, illinois 60505 phone: 630- 851- 4722 fax: 630- 851- 5040 www.conwin.com

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